The present application relates to an integrated circuit (IC) chip, and more particularly, to methods for improving mechanical strength of back-end-of-line (BEOL) dielectrics to prevent crack propagation within interconnect stacks.
Integrated circuits are generally created by forming an array of electronic devices (i.e., transistors, diodes, resistors, capacitors, etc.) and interconnect wiring structures on a semiconductor substrate. Generally, semiconductor devices and gates are formed in a first layer during front-end-of-line (FEOL) processing, followed by formation of interconnect wiring structures in a second layer by BEOL processes. These first and second layers can each contain multiple layers of dielectric material which electrically isolate the devices and interconnect structures. Advanced semiconductor processes utilize dielectric materials with low dielectric constants (low-k) to minimize interconnect parasitic capacitances.
After a plurality of integrated circuits (ICs) are formed on a semiconductor wafer, the semiconductor wafer is subjected to a wafer cutting process so as to divide the semiconductor wafer into a plurality of semiconductor chips. The semiconductor chip is then bonded to a substrate package. Due to poor mechanical strength of the low-k dielectric materials during the wafer cutting and bonding processes, cracks can form and propagate through the BEOL dielectrics toward the active area of the IC chip, causing chip failure. There thus exists a need to enhance mechanical strength of the BEOL dielectrics.